Frequency references provided by oscillators are required in every clocked electronic system, including communication circuits, microprocessors, and signal processing circuits. Oscillators frequently consist of high performance piezoelectric crystals, such as quartz oscillators. The advantages of quartz oscillators are their stable operating frequency and high quality factor. However, the disadvantages of quartz oscillators are their relatively large size and unsuitability for high integration with electronic circuitry (e.g., CMOS circuits). To address these limitations of quartz oscillators, integrated clock chips have been developed to perform various clock generation functions, which can frequently substitute for multiple quartz oscillators within an integrated circuit system.
Unfortunately, in contrast to crystal oscillators, which can automatically shut off in the absence of stimulus, clock chips typically maintain at least one clock as active even when an integrated circuit device(s) receiving the clock has entered a power-down mode of operation. Accordingly, systems using integrated clock chips may consume excessive levels of power during power-down modes of operation relative to otherwise equivalent systems using one or more quartz-based oscillators.
One example of an integrated circuit system that is configured to suspend clock generation during a standby mode of operation is disclosed in U.S. Pat. No. 7,071,768 to Abe et al. Another example of an integrated circuit system that is configured to support power conservation during standby modes of operation is disclosed by FIGS. 36-40 of U.S. Pat. No. 8,095,813 to Pernia et al., entitled “integrated Circuit Systems Having Processor-Controlled Clock Signal Generators Therein That Support Efficient Power Management,” the disclosure of which is hereby incorporated herein by reference. In particular, FIG. 36 of the '813 patent to Pernia et al. discloses input and output terminals 1205, 1210 of an integrated circuit 180 that receive and generate respective clocks having opposite phases (e.g., 180° out-of-phase). As shown by FIG. 36, an inverting buffer 1225 may be provided to generate an outgoing clock at output terminal (XOUT) 1210 in response to an incoming clock received at input terminal (XIN) 1205. This incoming clock may be generated by an up-stream clock generating apparatus 1100. The inverting buffer 1225 may be configured as illustrated by FIG. 1E herein, where the output signal X2—5 is generated in response to the input signal X1—5 when the buffer is “ON” (Case 5).
Moreover, as will be understood by those skilled in the art, the periodic nature of the outgoing clock may be suspended in response to a power-down mode of operation within the integrated circuit 180, which may suspend power to the inverting buffer 1225. Nonetheless, because the inverting buffer 1225 may enter one of a plurality of potential “inactive” states as illustrated by FIGS. 1A-1D (Case 1-Case 4), providing a periodic clock to the input terminal (e.g., X1—1, X1—2, X1—3 or X1—4) of the integrated circuit 180 may yield an undesired periodic or other fluctuating-type signal at the output terminal (e.g., X2—1, X2—2, X2—3 or X2—4), which may preclude detection of the power-down status of the integrated circuit 180 by the apparatus 1100.